Integrated electrochemical deposition of copper metallization for ultralarge-scale integrated circuits

• Published in: Journal of the Electrochemical Society 2004, Vol.151 (1), p.C81-C88
• Main Authors: CHANG, Shou-Yi, LIN, Chi-Wei, HSU, Hong-Hui, FANG, Jui-Hua, LIN, Su-Jien
• Format: Article
• Language: English
• Subjects: Applied sciences; Cross-disciplinary physics: materials science; rheology; Design. Technologies. Operation analysis. Testing; Electrodeposition, electroplating; Electronics; Exact sciences and technology; Integrated circuits; Materials science; Methods of deposition of films and coatings; film growth and epitaxy; Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
• ISSN: 0013-4651; 1945-7111
• DOI: 10.1149/1.1632478

An electrochemical deposition process for copper (Cu) metallization has been developed and investigated by the integration of nanoscaled palladium (Pd) catalyzation, electroless plating of Cu seed layers, and electroplating of Cu films in this study. Following surface cleaning and etching, sensitization and activation of Si/SiO(2) /TaN substrates were performed to obtain uniformly distributed Pd catalysts of only about 10 nm. Smooth and continuous 30 nm thick Cu seed layers with low electrical resistivity were electrolessly deposited using the nanosized Pd catalysts as nucleation sites. Copper metallization with high purity, small surface roughness, low electrical resistivity of 1.77 *m*W cm, low residual stresses, and good adhesion to substrates was achieved using the subsequent electroplating on the electroless seed layers and postannealing. Good gap-filling capability on finely patterned structures was performed and exhibited the great application potential of low-temperature integrated electrochemical deposition process for next-generation Cu metallization of ultra large-scale integrated circuits.