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Harmonic distortion caused by capacitors implemented with MOSFET gates
The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Exper...
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Published in: | IEEE journal of solid-state circuits 1992-10, Vol.27 (10), p.1470-1475 |
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Language: | English |
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container_end_page | 1475 |
container_issue | 10 |
container_start_page | 1470 |
container_title | IEEE journal of solid-state circuits |
container_volume | 27 |
creator | Behr, A.T. Schneider, M.C. Filho, S.N. Montoro, C.G. |
description | The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD |
doi_str_mv | 10.1109/4.156456 |
format | article |
fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_miscellaneous_28289151</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>156456</ieee_id><sourcerecordid>28903321</sourcerecordid><originalsourceid>FETCH-LOGICAL-c335t-92d8a1caba13a22fa0fd6fed2802809847d52977b12d25a265ec588e9aa899913</originalsourceid><addsrcrecordid>eNqNkMtLAzEQxoMoWKvg2dMeRLxszWOzmxxFrBUqPajgbZkmsxrZl8kW6X9vyha9CgPz-H58zAwh54zOGKP6JpsxmWcyPyATJqVKWSHeDsmEUqZSzSk9JichfMY2yxSbkPkCfNO1ziTWhaHzg-vaxMAmoE3W21j1YFych8Q1fY0NtkNUvt3wkTytnuf3L8k7DBhOyVEFdcCzfZ6S16jdLdLl6uHx7naZGiHkEBewCpiBNTABnFdAK5tXaLmiMbTKCiu5Loo145ZL4LlEI5VCDaC01kxMydXo2_vua4NhKBsXDNY1tNhtQsmVpkLw_4ARZXIHXo-g8V0IHquy964Bvy0ZLXcfLbNy_GhEL_eeEAzUlYfWuPDLZ_FErkTELkbMIeKf2-jxA0vqfE4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28289151</pqid></control><display><type>article</type><title>Harmonic distortion caused by capacitors implemented with MOSFET gates</title><source>IEEE Xplore (Online service)</source><creator>Behr, A.T. ; Schneider, M.C. ; Filho, S.N. ; Montoro, C.G.</creator><creatorcontrib>Behr, A.T. ; Schneider, M.C. ; Filho, S.N. ; Montoro, C.G.</creatorcontrib><description>The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD <-40 dB for a 3-V voltage swing).< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.156456</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Capacitance ; CMOS process ; CMOS technology ; Design. Technologies. Operation analysis. Testing ; Digital systems ; Electronics ; Exact sciences and technology ; Filters ; Harmonic distortion ; Integrated circuits ; MOS capacitors ; MOSFET circuits ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Very large scale integration ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1992-10, Vol.27 (10), p.1470-1475</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c335t-92d8a1caba13a22fa0fd6fed2802809847d52977b12d25a265ec588e9aa899913</citedby><cites>FETCH-LOGICAL-c335t-92d8a1caba13a22fa0fd6fed2802809847d52977b12d25a265ec588e9aa899913</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/156456$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4335283$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Behr, A.T.</creatorcontrib><creatorcontrib>Schneider, M.C.</creatorcontrib><creatorcontrib>Filho, S.N.</creatorcontrib><creatorcontrib>Montoro, C.G.</creatorcontrib><title>Harmonic distortion caused by capacitors implemented with MOSFET gates</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD <-40 dB for a 3-V voltage swing).< ></description><subject>Applied sciences</subject><subject>Capacitance</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital systems</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Filters</subject><subject>Harmonic distortion</subject><subject>Integrated circuits</subject><subject>MOS capacitors</subject><subject>MOSFET circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Very large scale integration</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1992</creationdate><recordtype>article</recordtype><recordid>eNqNkMtLAzEQxoMoWKvg2dMeRLxszWOzmxxFrBUqPajgbZkmsxrZl8kW6X9vyha9CgPz-H58zAwh54zOGKP6JpsxmWcyPyATJqVKWSHeDsmEUqZSzSk9JichfMY2yxSbkPkCfNO1ziTWhaHzg-vaxMAmoE3W21j1YFych8Q1fY0NtkNUvt3wkTytnuf3L8k7DBhOyVEFdcCzfZ6S16jdLdLl6uHx7naZGiHkEBewCpiBNTABnFdAK5tXaLmiMbTKCiu5Loo145ZL4LlEI5VCDaC01kxMydXo2_vua4NhKBsXDNY1tNhtQsmVpkLw_4ARZXIHXo-g8V0IHquy964Bvy0ZLXcfLbNy_GhEL_eeEAzUlYfWuPDLZ_FErkTELkbMIeKf2-jxA0vqfE4</recordid><startdate>19921001</startdate><enddate>19921001</enddate><creator>Behr, A.T.</creator><creator>Schneider, M.C.</creator><creator>Filho, S.N.</creator><creator>Montoro, C.G.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>19921001</creationdate><title>Harmonic distortion caused by capacitors implemented with MOSFET gates</title><author>Behr, A.T. ; Schneider, M.C. ; Filho, S.N. ; Montoro, C.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c335t-92d8a1caba13a22fa0fd6fed2802809847d52977b12d25a265ec588e9aa899913</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Applied sciences</topic><topic>Capacitance</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital systems</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Filters</topic><topic>Harmonic distortion</topic><topic>Integrated circuits</topic><topic>MOS capacitors</topic><topic>MOSFET circuits</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Very large scale integration</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Behr, A.T.</creatorcontrib><creatorcontrib>Schneider, M.C.</creatorcontrib><creatorcontrib>Filho, S.N.</creatorcontrib><creatorcontrib>Montoro, C.G.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Behr, A.T.</au><au>Schneider, M.C.</au><au>Filho, S.N.</au><au>Montoro, C.G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Harmonic distortion caused by capacitors implemented with MOSFET gates</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1992-10-01</date><risdate>1992</risdate><volume>27</volume><issue>10</issue><spage>1470</spage><epage>1475</epage><pages>1470-1475</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD <-40 dB for a 3-V voltage swing).< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.156456</doi><tpages>6</tpages></addata></record> |
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language | eng |
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source | IEEE Xplore (Online service) |
subjects | Applied sciences Capacitance CMOS process CMOS technology Design. Technologies. Operation analysis. Testing Digital systems Electronics Exact sciences and technology Filters Harmonic distortion Integrated circuits MOS capacitors MOSFET circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Very large scale integration Voltage |
title | Harmonic distortion caused by capacitors implemented with MOSFET gates |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T04%3A15%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Harmonic%20distortion%20caused%20by%20capacitors%20implemented%20with%20MOSFET%20gates&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Behr,%20A.T.&rft.date=1992-10-01&rft.volume=27&rft.issue=10&rft.spage=1470&rft.epage=1475&rft.pages=1470-1475&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.156456&rft_dat=%3Cproquest_ieee_%3E28903321%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c335t-92d8a1caba13a22fa0fd6fed2802809847d52977b12d25a265ec588e9aa899913%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=28289151&rft_id=info:pmid/&rft_ieee_id=156456&rfr_iscdi=true |