A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-/spl mu/m CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2002-05, Vol.37 (5), p.536-542
Main Authors: Koo, Yido, Huh, Hyungki, Cho, Yongsik, Lee, Jeongwoo, Park, Joonbae, Lee, Kyeongho, Jeong, Deog-Kyoon, Kim, Wonchan
Format: Article
Language:English
Subjects:
1f noise
Channel spacing
Channels
Charge pumps
Circuits
CMOS
CMOS technology
Filters
Frequency synthesizers
Gain
Noise
Noise level
Power dissipation
Tuning
Voltage-controlled oscillators
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Summary:A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-/spl mu/m CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.997845