A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 /spl mu/m CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1994-04, Vol.29 (4), p.397-402
Main Authors: Fattaruso, J.W., Mahant-Shetti, S.S., Barton, J.B.
Format: Article
Language:English
Subjects:
Analog computers
Analog-digital conversion
CMOS process
Computer interfaces
Concurrent computing
Engines
Fuzzy logic
Logic arrays
Random access memory
Read-write memory
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Summary:A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 /spl mu/m CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 /spl mu/s.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.280687