Faulty behavior of storage elements and its effects on sequential circuits

It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here....

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 1993-12, Vol.1 (4), p.446-452
Main Authors: Al-Assadi, W.K., Malaiya, Y.K., Jayasumana, A.P.
Format: Article
Language:English
Subjects:
Circuit faults
Circuit testing
Clocks
Digital circuits
Electrical fault detection
Fault detection
Logic circuits
Logic testing
Physics computing
Sequential circuits
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Summary:It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered.< >
ISSN:1063-8210
1557-9999
DOI:10.1109/92.250192