A flexible multiport RAM compiler for data path

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0- mu m CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both la...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1991-03, Vol.26 (3), p.343-349
Main Authors: Shinohara, H., Matsumoto, N., Fujimori, K., Tsujihashi, Y., Nakao, H., Kato, S., Horiba, Y., Tada, A.
Format: Article
Language:English
Subjects:
Circuits
CMOS technology
Digital signal processors
Energy consumption
Helium
Inverters
Microprocessors
Random access memory
Read-write memory
Throughput
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Summary:A multiport RAM compiler with flexible layout and port organization has been developed using 1.0- mu m CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b*2048 words and 72 b*512 words was also obtained. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1 K and 11.0 ns for 32 K.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.75013