Fast CMOS ECL receivers with 100-mV worst-case sensitivity

CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cove...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1988-02, Vol.23 (1), p.59-67
Main Authors: Chappell, B.A., Chappell, T.I., Schuster, S.E., Segmuller, H.M., Allan, J.W., Franch, R.L., Restle, P.J.
Format: Article
Language:English
Subjects:
Circuit simulation
Circuit testing
CMOS logic circuits
CMOS technology
Delay
Differential amplifiers
Feedback
Inverters
Power supplies
Random access memory
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Summary:CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.257