A high-speed sample-and-hold technique using a Miller hold capacitance

• Published in: IEEE journal of solid-state circuits 1991-04, Vol.26 (4), p.643-651
• Main Authors: Lim, P.J., Wooley, B.A.
• Format: Article
• Language: English
• Subjects: Applied sciences; Capacitance; Circuits; Clocks; CMOS technology; Delay; Electronics; Exact sciences and technology; Feedback; Prototypes; Sampling methods; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switches; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.75067

A circuit technique is introduced for increasing the precision of an open-loop sample-and-hold circuit without significantly reducing the sampling speed. With this technique, the sampling error resulting from input-dependent charge injection of the sampling switch is significantly attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the transition to the hold mode through the action of Miller feedback. The technique thus allows for a high sampling speed without the precision penalty traditionally associated with open-loop sample-and-hold circuits. A sample-and-hold circuit based on the proposed approach has been designed and fabricated in a 1- mu m CMOS technology, and an order-of-magnitude of reduction in the input-dependent charge injection has been demonstrated experimentally. This prototype circuit is capable of sampling an input to a precision of 8 b with an acquisition time of 5 ns. The experimental sample-and-hold circuit operates from a single 5-V supply and dissipates 26.5 mW.< >