Low-power encodings for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 1997-12, Vol.5 (4), p.444-455
Main Authors: Stan, M.R., Burleson, W.P.
Format: Article
Language:English
Subjects:
Applied sciences
CMOS technology
Communication switching
Design. Technologies. Operation analysis. Testing
Electronics
Encoding
Energy consumption
Exact sciences and technology
Global communication
Integrated circuits
Power dissipation
Process design
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Space technology
Very large scale integration
Voltage
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Summary:Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling.
ISSN:1063-8210
1557-9999
DOI:10.1109/92.645071