High-speed, low-switching noise CMOS memory data output buffer

This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving o...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1994-11, Vol.29 (11), p.1359-1365
Main Authors: Chioffi, E., Maloberti, F., Marchesi, G., Torelli, G.
Format: Article
Language:English
Subjects:
Capacitors
Circuit noise
Delay
Energy consumption
EPROM
Noise generators
Noise reduction
Packaging
Power supplies
Voltage
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Summary:This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving of the output pull-up and pull-down transistors. Tristate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm/sup 2/ and ensures a better than 15 ns output transition time with a load capacitor of 100 pF.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.328637