Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2003-04, Vol.50 (4), p.959-966
Main Authors: Mohapatra, N.R., Desai, M.P., Narendra, S.G., Ramgopal Rao, V.
Format: Article
Language:English
Subjects:
Capacitance
Monte Carlo methods
MOSFETs
Permittivity
Semiconductor device modeling
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Summary:In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2003.811387