Low-temperature CMOS 8 x 8 bit multipliers with sub-10-ns speeds

Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1987-01, Vol.ED-34 (1), p.94-100
Main Authors: Hanamura, S, Aoki, M, Masuhara, T, Minato, O, Sakai, Y, Hayashida, T
Format: Article
Language:English
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Summary:Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, multipliers with two different circuit configurations are designed and fabricated with a gate length of 1.3 microns. Multiplication speeds of 8.0 and 6.6 ns are obtained with CMOS circuit configurations at 4.2 K and with pulsed-p-load/CMOS circuit configurations at 77 K, respectively. (Author)
ISSN:0018-9383