Simulating the behavior of software modules by trace rewriting

The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, we plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the extern...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on software engineering 1994-10, Vol.20 (10), p.750-759
Main Authors: Yabo Wang, Parnas, D.L.
Format: Article
Language:English
Subjects:
Automata
Computational modeling
Discrete event simulation
Equations
Formal specifications
Mathematical models
Programming
Simulation
Software
Software development management
Software systems
Software tools
Specifications
Studies
System testing
Systems development
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, we plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. We first present the trace assertion method. Then we formally define trace rewriting systems and show how trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation.< >
ISSN:0098-5589
1939-3520
DOI:10.1109/32.328996