SPEED: Stand-alone programmable ethernet enabled devices

• Published in: Microprocessors and microsystems 2004-09, Vol.28 (7), p.387-399
• Main Authors: Elkeelany, O., Chaudhry, G.
• Format: Article
• Language: English
• Subjects: Hardware description language; Low power design; Network ready devices; Simulation; Synthesis
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2004.03.020

In this paper we present the design and synthesis of Standalone Programmable Ethernet Enabled Devices (SPEED) as a low cost and power consumption embedded system, which also include an Electrical Erasable Programmable Read Only Memory controller for configurable address assignments. The main function of SPEED is to eliminate the operating system processing of network protocol stack running by personal computer processor and simplifying network functions. This simplification is not exclusively required to fit in a hardware solution, but more important it improves network performance. It utilizes the concept of network channels, where Ethernet frames are delivered through a custom multicast addressing scheme. After validating SPEED simulation outputs, we synthesize the design in FPGA chip using Verilog HDL. Performance measures like power consumption and area utilization are computed using Verilog HDL synthesis tools. Initial performance measures had shown that the SPEED would be reducing the power consumption. Consequently, network devices could be powered through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. This way, SPEED reduces the installation complexity, especially for large number of devices (e.g. surveillance cameras).