Analysis of flip-chip packaging challenges on copper/low-k interconnects

An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been used to bridge the scale difference between the flip-chip packages and the metal/dielectric stacks. To...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on device and materials reliability 2003-12, Vol.3 (4), p.111-118
Main Authors: Mercado, L.L., Goldberg, C., Kuo, S.-M., Tien-Yu, Tom Lee, Pozder, S.K.
Format: Magazinearticle
Language:English
Subjects:
Adhesives
AGING MECHANISMS
Capacitance
CHIPS
Conductivity
CONNECTORS (ELECTRICAL)
Copper
Crosstalk
Delay
Devices
Dielectric materials
Dielectrics
ELECTRONIC PRODUCTS
FAILURE
Guidelines
Integrated circuit interconnections
Packages
PACKAGING
Polymer films
Risk
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been used to bridge the scale difference between the flip-chip packages and the metal/dielectric stacks. To achieve a smaller feature size and higher speed in future chips, SiO/sub 2/ can be replaced with low-k dielectric material in all via and trench layers or the number of metal layers can be increased. The effect of both packaging options has been evaluated. With either option, the future flip-chip copper/low-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provides a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flip-chip packages.
ISSN:1530-4388
1558-2574
DOI:10.1109/TDMR.2003.821541