Analysis of the effects of scaling on interconnect delay in ULSI circuits

• Published in: IEEE transactions on electron devices 1993-03, Vol.40 (3), p.591-597
• Main Authors: Bothra, S., Rogers, B., Kellam, M., Osburn, C.M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Capacitance; CMOS logic circuits; Current density; Delay effects; Design. Technologies. Operation analysis. Testing; Dielectric constant; Dielectric materials; Electromigration; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switching circuits; Ultra large scale integration
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.199365

A model has been developed to assess interconnect delay in ULSI circuits as dimensions are scaled deep into the submicrometer regime. In addition to RC delay, the model includes the effects of current density limitations imposed to prevent electromigration of the interconnect metallurgy. The authors confirm that interconnect delays will contribute significantly to the total circuit delay in future ULSI circuits unless improvements are implemented. However, contrary to previous reports, the authors show that lowering the resistivity of the interconnect will not result in significant improvements in interconnect switching speed. Only by introducing lower dielectric constant interlevel insulators or by improving the electromigration resistance of the interconnect can significant performance enhancements be realized.< >