An analytical model for the gate capacitance of small-geometry MOS structures

An analytical formulation of the gate capacitance of MOS structures which takes into consideration the effects of electrode thickness and lateral gate dimensions is presented. Results are presented in normalized form covering a wide range of typical device dimensions.

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Bibliographic Details
Published in:IEEE transactions on electron devices 1983-12, Vol.30 (12), p.1838-1839
Main Author: Greeneich, E.W.
Format: Article
Language:English
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Description
Summary:An analytical formulation of the gate capacitance of MOS structures which takes into consideration the effects of electrode thickness and lateral gate dimensions is presented. Results are presented in normalized form covering a wide range of typical device dimensions.
ISSN:0018-9383
1557-9646
DOI:10.1109/T-ED.1983.21456