On the design of selective coefficient DCT module

An innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. I...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 1998-04, Vol.8 (2), p.143-146
Main Authors: LU, C.-Y, WEN, K.-A
Format: Article
Language:English
Subjects:
Applied sciences
Bandwidth
Circuits
Computer architecture
Delay
Discrete cosine transforms
Electronics
Exact sciences and technology
Image coding
Information, signal and communications theory
Integrated circuits
Integrated circuits by function (including memories and processors)
Mathematical methods
Matrix decomposition
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Telecommunications and information theory
Two dimensional displays
Video compression
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Summary:An innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. It can save the transposition delay to simplify the computation flow of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient.
ISSN:1051-8215
1558-2205
DOI:10.1109/76.664099