A novel hierarchical-search block matching algorithm and VLSI architecture considering the spatial complexity of the macroblock

We propose a novel hierarchical-search block matching algorithm for motion estimation, which adaptively selects an initial search level based on the spatial complexity of a matching block. It relies on a simple computation of the pixel intensity variation in the current macroblock. We demonstrate it...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 1998-05, Vol.44 (2), p.337-342
Main Authors: Han, Tae-Hee, Hwang, Seung Ho
Format: Article
Language:English
Subjects:
CMOS technology
Computational efficiency
Computer architecture
Hardware
High definition video
Image coding
Image sequences
Motion estimation
Spatial resolution
Very large scale integration
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Summary:We propose a novel hierarchical-search block matching algorithm for motion estimation, which adaptively selects an initial search level based on the spatial complexity of a matching block. It relies on a simple computation of the pixel intensity variation in the current macroblock. We demonstrate its effectiveness in two aspects: the performance and the computational cost. A hardware architecture and a VLSI realization of this algorithm with half-pel motion estimation and motion compensation are also presented. The proposed algorithm greatly reduces the computations required in the existing hierarchical-search block matching algorithms while achieves virtually identical performance to them.
ISSN:0098-3063
1558-4127
DOI:10.1109/30.681947