An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process toleranc...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 1994-11, Vol.29 (11), p.1303-1309
Main Authors: Asakura, M., Ooishi, T., Tsukude, M., Tomishima, S., Eimori, T., Hidaka, H., Ohno, Y., Arimoto, K., Fujishima, K., Nishimura, T., Yoshihara, T.
Format: Article
Language:English
Subjects:
Costs
Energy consumption
Fabrication
Leakage current
Power generation
Production
Random access memory
Semiconductor devices
Semiconductor memory
Threshold voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm/sup 2/ and a performance of 34 ns access time.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.328628