On the assumptions contained in semiconductor yield models

It is shown that the form of semiconductor yield models, and their predictions, are to a large extent affected by the size distribution of all defects and the spatial distribution of fatal defects. As the effects of these and other assumptions on yield models are rarely described in the literature,...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 1992-08, Vol.11 (8), p.966-975
Main Author: Ferris-Prabhu, A.V.
Format: Article
Language:English
Subjects:
Analytical models
Applied sciences
Costs
Design. Technologies. Operation analysis. Testing
Electronics
Electronics industry
Equations
Exact sciences and technology
Gallium arsenide
Integrated circuits
Logic design
Metallization
Predictive models
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Virtual manufacturing
Yield estimation
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Summary:It is shown that the form of semiconductor yield models, and their predictions, are to a large extent affected by the size distribution of all defects and the spatial distribution of fatal defects. As the effects of these and other assumptions on yield models are rarely described in the literature, the author examines them and develops scaling rules for the average number of fatal defects per chip. To trace differences in the predicted yield to the various assumptions, the treatment compares a simple Poisson model with a compound Poisson model and shows that, when appropriate scaling rules are used, yield predictions of the simple Poisson model are accurate for a new product with chips with areas up to an order of magnitude larger than chips of existing products.< >
ISSN:0278-0070
1937-4151
DOI:10.1109/43.149768