Physical design guides for substrate noise reduction in CMOS digital circuits

Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-/spl mu/V 100-ps resolution substrate noise measurements of controlled substrate noises by a transition-controllable noise source and practical substrate noises under CMOS logic operations. The...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2001-03, Vol.36 (3), p.539-549
Main Authors: Nagata, M., Nagai, J., Hijikata, K., Morie, T., Iwata, A.
Format: Article
Language:English
Subjects:
Circuit noise
Circuits
CMOS
CMOS integrated circuits
CMOS logic circuits
Current supplies
Effectiveness
Estimators
Integrated circuit noise
Large scale integration
Logic
Noise
Noise measurement
Noise reduction
Parasitic capacitance
Semiconductor device modeling
Waveforms
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Summary:Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-/spl mu/V 100-ps resolution substrate noise measurements of controlled substrate noises by a transition-controllable noise source and practical substrate noises under CMOS logic operations. The noise injection is dominated by leaks of supply/return bounce into the substrate, and the noise intensity is determined by logic transition activity, according to experimental observations. A time-series divided parasitic capacitance model is derived as an efficient estimator of the supply current for simulating the substrate noise injection and can reproduce the measured substrate noise waveforms. The efficacy of physical noise reduction techniques at the layout and circuit levels is quantified and limitations are discussed in conjunction with the noise injection mechanisms. The reduced supply bounce CMOS circuit is proposed as a universal noise reduction technique, and more than 90% noise reduction to conventional CMOS is demonstrated.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.910494