Operational analysis of synchrotron-based X-ray lithography: comparison of 200 mm and 300 mm wafer flows

• Published in: IEEE transactions on electronics packaging manufacturing 2000-10, Vol.23 (4), p.328-336
• Main Authors: White, K.P., Trybula, W.J.
• Format: Article
• Language: English
• Subjects: Acceptability; Computer simulation; Discrete event simulation; Frequency estimation; Lithography; Mathematical analysis; Mathematical models; Performance analysis; Process design; Productivity; Semiconductor device modeling; State estimation; Synchrotron radiation; Throughput; Wafers; X-ray lithography; X-rays
• ISSN: 1521-334X; 1558-0822
• DOI: 10.1109/6104.895079

A companion paper describes a discrete-event simulation model that captures the processing of wafers through a next-generation X-ray lithography area employing multiple synchrotrons as the source of exposure radiation. The model incorporates the best current information on unit-cell design and processing times; implements the spectrum of events that interrupt the flow of wafers processing on the cell; and provides estimates of weekly throughput for the cell and the frequency of SEMI E-10 equipment states for the corresponding exposure tool. In this paper we apply the model to compare the performance of cells fabricating 200 mm wafers with that of cells fabricating 300 mm wafers. Results illustrate the dependence of average wafer throughput on lot size, exposure times, and assumptions regarding the number of die per wafer. For fixed assumptions regarding differential lot sizes for different wafer diameters, maximum throughput of wafers is achieved for 200 mm wafers with 25/spl times/25 mm field size. Ignoring wafer-sort losses, however, a maximum throughput of chips is realized for 300 mm wafers with 22/spl times/22 mm fields with 11/spl times/22 devices. Remarkably, the distribution of equipment states remains relatively unchanged across simulation experiments. These results suggest a useful analytical approximation for cell performance. When calibrated against the simulation results, this static model reinforces the conclusion that, all else being equal, acceptable throughput can be achieved for 300 mm wafers using the smaller wafer lots required to maintain acceptable cycle times.