Stress testing FET gates without the use of test patterns

A test technique is described for stressing each FET gate in multiphase dynamic random logic FET circuits incorporated in a large-scale integrated (LSI) device. This 100 percent gate stressing essentially results from sequencing the clock signals in reverse order to that sequence required to transfe...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1975-10, Vol.10 (5), p.294-298
Main Author: Puri, Y.
Format: Article
Language:English
Subjects:
Circuit testing
Clocks
Failure analysis
FET circuits
Large scale integration
Logic circuits
Logic devices
Logic functions
Logic testing
Stress
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Description
Summary:A test technique is described for stressing each FET gate in multiphase dynamic random logic FET circuits incorporated in a large-scale integrated (LSI) device. This 100 percent gate stressing essentially results from sequencing the clock signals in reverse order to that sequence required to transfer information through the logic paths to perform the circuit logic functions. When the clock signals are run in this reverse order, no input test patterns are required. Stressing by this method helps guarantee the reliability of shipped devices by preventing the shipment of possible bad lots or devices which are likely to fail in the field due to device failure mechanisms such as sodium ion migration and/or gate breakdown.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1975.1050614