Radiation-hardened silicon-on-insulator junction field-effect transistors fabricated by a self-aligned process

A self-aligned process has been developed for fabricating JFET's in zone-melting-recrystallized (ZMR) Si films on SiO 2 -coated Si substrates. This process has been used to fabricate n-JFET's exhibiting transconductance values up to 63 mS/mm. For 228 devices within an area of about 4 × 4 c...

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Bibliographic Details
Published in:IEEE electron device letters 1987-03, Vol.8 (3), p.101-103
Main Authors: Choi, H.K., Bor-Yeu Tsaur, Chen, C.K.
Format: Article
Language:English
Subjects:
Applied sciences
Boron
Degradation
Doping
Electronics
Exact sciences and technology
Fabrication
FETs
Leakage current
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductor films
Silicon on insulator technology
Threshold voltage
Transconductance
Transistors
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Summary:A self-aligned process has been developed for fabricating JFET's in zone-melting-recrystallized (ZMR) Si films on SiO 2 -coated Si substrates. This process has been used to fabricate n-JFET's exhibiting transconductance values up to 63 mS/mm. For 228 devices within an area of about 4 × 4 cm 2 , the mean threshold voltage is 578 mV and the standard deviation is 22 mV. With a -15-V bias applied to the Si substrate during irradiation and device operation, the devices show low threshold voltage shift (< -75 mV) and small transconductance degradation (∼30 percent) for exposure to total-dose radiation of 10 8 rad(Si).
ISSN:0741-3106
1558-0563
DOI:10.1109/EDL.1987.26566