Error suppressing encode logic of FCDL in a 6-b flash A/D converter

A 6-b, 166-Ms/s BiCMOS flash A/D converter was fabricated using a folded cascoded differential logic (FCDL). This FCDL reduces glitch errors caused by comparator metastability and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7-/spl mu/m, f/sub t/=12 GHz BiC...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1997-09, Vol.32 (9), p.1460-1464
Main Authors: Ono, K., Matsuura, T., Imaizumi, E., Okazawa, H., Shimokawa, R.
Format: Article
Language:English
Subjects:
BiCMOS integrated circuits
Circuit noise
Encoding
Error analysis
Logic
Metastasis
Reflective binary codes
Semiconductor device measurement
Semiconductor device noise
Signal to noise ratio
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Summary:A 6-b, 166-Ms/s BiCMOS flash A/D converter was fabricated using a folded cascoded differential logic (FCDL). This FCDL reduces glitch errors caused by comparator metastability and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7-/spl mu/m, f/sub t/=12 GHz BiCMOS was less than 10/sup -10/ times/sample. Without power-consuming highspeed track and hold circuit, the FCDL achieved low error rate and low power consumption of 505 mW at a 5.0-V power supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.628765