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SEU/SRAM as a process monitor
The SEU/SRAM is a 4-kbit static random access memory (SRAM) designed to detect single-event upsets (SEU's) produced by high-energy particles, either in space or on the ground. This device was used to determine the distribution of the memory cell spontaneous flip potential. The variance in this...
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Published in: | IEEE transactions on semiconductor manufacturing 1994-08, Vol.7 (3), p.319-324 |
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container_title | IEEE transactions on semiconductor manufacturing |
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creator | Blaes, B.R. Buehler, M.G. |
description | The SEU/SRAM is a 4-kbit static random access memory (SRAM) designed to detect single-event upsets (SEU's) produced by high-energy particles, either in space or on the ground. This device was used to determine the distribution of the memory cell spontaneous flip potential. The variance in this potential was determined to be due to the variation in the threshold voltage of one of the n-FET's found in the memory cell. For a 1.2-/spl mu/m CMOS process, the standard deviation of the n-FET VT was found to be 8 mV. This structure provides substantial statistical data; 4096 data points are measured. Using cumulative distribution and residual plots, outlier cells, such as stuck cells and nonnormally distributed cells, are easily identified.< > |
doi_str_mv | 10.1109/66.311335 |
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This device was used to determine the distribution of the memory cell spontaneous flip potential. The variance in this potential was determined to be due to the variation in the threshold voltage of one of the n-FET's found in the memory cell. For a 1.2-/spl mu/m CMOS process, the standard deviation of the n-FET VT was found to be 8 mV. This structure provides substantial statistical data; 4096 data points are measured. Using cumulative distribution and residual plots, outlier cells, such as stuck cells and nonnormally distributed cells, are easily identified.< ></description><subject>Applied sciences</subject><subject>CMOS process</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Event detection</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Inverters</subject><subject>Monitoring</subject><subject>Radiation detectors</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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This device was used to determine the distribution of the memory cell spontaneous flip potential. The variance in this potential was determined to be due to the variation in the threshold voltage of one of the n-FET's found in the memory cell. For a 1.2-/spl mu/m CMOS process, the standard deviation of the n-FET VT was found to be 8 mV. This structure provides substantial statistical data; 4096 data points are measured. Using cumulative distribution and residual plots, outlier cells, such as stuck cells and nonnormally distributed cells, are easily identified.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/66.311335</doi><tpages>6</tpages></addata></record> |
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ispartof | IEEE transactions on semiconductor manufacturing, 1994-08, Vol.7 (3), p.319-324 |
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language | eng |
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source | IEEE Electronic Library (IEL) Journals |
subjects | Applied sciences CMOS process Design. Technologies. Operation analysis. Testing Electronics Event detection Exact sciences and technology Integrated circuits Inverters Monitoring Radiation detectors Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Single event upset SRAM chips Threshold voltage |
title | SEU/SRAM as a process monitor |
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