Serendipitous SEU hardening of resistive load SRAMs

High and low resistive load versions of Micron Technology's MT5C1008C (128K/spl times/8) and MT5C2561C (256K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 1996-06, Vol.43 (3), p.931-935
Main Authors: Koga, R., Kirshman, J.F., Pinkerton, S.D., Hansel, S.J., Crawford, K.B., Crain, W.R.
Format: Article
Language:English
Subjects:
Aerospace testing
CMOS memory circuits
CMOS technology
Computer errors
Computer simulation
MOSFETs
Random access memory
Single event upset
SRAM chips
Variable structure systems
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Summary:High and low resistive load versions of Micron Technology's MT5C1008C (128K/spl times/8) and MT5C2561C (256K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors was observed for the low resistive load SRAMs, which also exhibited a "1"/spl rarr/"0" to "0"/spl rarr/"1" bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.
ISSN:0018-9499
1558-1578
DOI:10.1109/23.510736