A single-chip digitally calibrated 5.15-5.825-GHz 0.18-mum CMOS transceiver for 802.11a wireless LAN

• Published in: IEEE journal of solid-state circuits 2003-12, Vol.38 (12), p.2221-2231
• Main Authors: Vassiliou, I, Vavelidis, K, Georgantas, T, Plevridis, S, Haralabidis, N, Kamoulakos, G, Kapnistis, C, Kavadias, S, Kokolakis, Y, Merakos, P, Rudell, J C, Yamanaka, A, Bouras, S, Bouras, I
• Format: Article
• Language: English
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2003.819086

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-mum CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8 deg rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm(2).