Reducing memory latency via read-after-read memory dependence prediction

We observe that typical programs exhibit highly regular read-after-read (RAR) memory dependence streams. To exploit this regularity, we introduce read-after-read memory dependence prediction. This technique predicts whether: 1) a load will access a memory location that a preceding load accesses and...

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Bibliographic Details
Published in:IEEE transactions on computers 2002-03, Vol.51 (3), p.313-326
Main Authors: Moshovos, A., Sohi, G.S.
Format: Article
Language:English
Subjects:
Bypasses
Delay
Experimentation
Graphs
Naming
Position (location)
Raw
Regularity
Streams
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Summary:We observe that typical programs exhibit highly regular read-after-read (RAR) memory dependence streams. To exploit this regularity, we introduce read-after-read memory dependence prediction. This technique predicts whether: 1) a load will access a memory location that a preceding load accesses and 2) exactly which this preceding load is. This prediction is done without actual knowledge of the corresponding memory addresses. We also present two techniques that utilize RAR memory dependence prediction to reduce memory latency. In the first technique, a load may obtain a value by naming a preceding load with which an RAR dependence is predicted. The second technique speculatively converts a series of LOAD/sub 1/-USE/sub 1/,...,LOAD/sub N/-USE/sub N/ chains into a single LOAD/sub 1/-USE/sub 1/...USE/sub N/ producer/consumer graph. Our techniques can be implemented as small extensions to the previously proposed read-after-write (RAW) dependence prediction-based speculative memory cloaking and speculative memory bypassing. Performance experimentation results of RAR-based techniques are provided.
ISSN:0018-9340
1557-9956
DOI:10.1109/12.990129