Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM

A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An exten...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1990-02, Vol.25 (1), p.61-67
Main Authors: Kuo, C., Toms, T., Neel, B.T., Jelemensky, J., Carter, E.A., Smith, P.
Format: Article
Language:English
Subjects:
Circuit analysis
Circuit faults
Circuit synthesis
Circuit testing
Electrical fault detection
Failure analysis
Fault detection
Microcontrollers
Random access memory
Temperature
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Summary:A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An extensive circuit analysis was made to establish the operation theory and special circuit design features required for SDD. Complete SDD circuits have been developed and implemented into a 16 K CMOS SRAM module for a 32-b microcontroller. Full operation and effectiveness of the SDD technique were verified from a special experimental 16 K CMOS RAM module with built-in defective cells. the SDD technique can accomplish not only the retention test at room temperature, but also the detection of other defects that were heretofore impractical to detect using the conventional retention test technique of high-temperature bakes and functional tests.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.50285