A single-chip I/sup 2/L PCM codec

A single chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the D3 specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made for zero code suppression and A/B signaling. Even with this sig...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1979-02, Vol.14 (1), p.59-64
Main Authors: Blauschild, R.A., Tucci, P.A., Russell, H.T., Purinton, D.M., Murthi, E.N.
Format: Article
Language:English
Subjects:
Circuit noise
Clocks
Codecs
Decoding
Encoding
Logic design
Phase change materials
Production
Registers
Switches
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Description
Summary:A single chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the D3 specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made for zero code suppression and A/B signaling. Even with this signaling, the codec achieves a worst case idle channel noise of 13 dBrnC0.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1979.1051142