A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2000-10, Vol.35 (10), p.1498-1501
Main Authors: Kawaguchi, H., Nose, K., Sakurai, T.
Format: Article
Language:English
Subjects:
Batteries
CMOS
CMOS logic circuits
Cut-off
Delay
Electric potential
Gates
High speed
Leakage current
Libraries
Logic circuits
Logic gates
MOS devices
MOSFETs
Very large scale integration
Voltage
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Summary:A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.871328