Synthesis of delay-verifiable combinational circuits

We address the problem of testing circuits for temporal correctness. A circuit is considered delay-verifiable if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more...

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Bibliographic Details
Published in:IEEE transactions on computers 1995-02, Vol.44 (2), p.213-222
Main Authors: Ke, W., Menon, P.R.
Format: Article
Language:English
Subjects:
Circuit faults
Circuit synthesis
Circuit testing
Combinational circuits
Delay effects
Electrical fault detection
Robustness
Sufficient conditions
Timing
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Summary:We address the problem of testing circuits for temporal correctness. A circuit is considered delay-verifiable if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more than one path delay fault. We provide a general framework for examining delay-verifiability by introducing a special class of faults called primitive path delay faults. It is necessary and sufficient to test every fault in this class to ensure the temporal correctness of combinational circuits. Based on this result, we develop a synthesis procedure for combinational circuits that can be tested for correct timing. Experimental data show that such implementations usually require less area than completely delay testable implementations.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.364533