A voltage reduction technique for battery-operated systems

Two techniques for voltage reduction are presented, both of which can significantly reduce the power consumption of digital CMOS circuits. The fixed reduction of voltage is applicable to small systems with a low initial consumption, however, the optimum voltage is not reached and the correct operati...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1990-10, Vol.25 (5), p.1136-1140
Main Authors: Von Kaenel, V., Macken, P., Degrauwe, M.G.R.
Format: Article
Language:English
Subjects:
Digital circuits
Energy consumption
Geometry
Instruments
Portable computers
Power system reliability
Temperature
Very large scale integration
Voltage
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Summary:Two techniques for voltage reduction are presented, both of which can significantly reduce the power consumption of digital CMOS circuits. The fixed reduction of voltage is applicable to small systems with a low initial consumption, however, the optimum voltage is not reached and the correct operation of the circuit is not guaranteed. The self-adjusted reduction of voltage is adapted to bigger digital systems. The correct operation of the digital circuit is guaranteed, and the supply voltage is near the optimum for the speed requirements. This technique is more versatile, accurate, and reliable than the fixed one.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.62134