Wideband compressive receiver based on advanced superconductor and semiconductor circuits

A novel compressive cryoreceiver architecture has been proposed combining analog HTS, cryoelectronic, and advanced high-speed GaAs and high-speed/low-power SOI CMOS semiconductor technologies. The proposed receiver will rival the sensitivity of narrowband receivers while providing unprecedented wide...

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Bibliographic Details
Published in:IEEE transactions on applied superconductivity 1997-06, Vol.7 (2), p.2462-2467
Main Authors: Lyons, W.G., Arsenault, D.R., Keast, C.L., Shaver, D.C., Berger, R., Anderson, A.C., Murphy, P.G., Sollner, T.C.L.G., Ralston, R.W.
Format: Article
Language:English
Subjects:
Applied sciences
Bandwidth
Chirp
Circuit properties
CMOS technology
Dispersion
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Filters
Frequency
Gallium arsenide
High temperature superconductors
Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits
Narrowband
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Superconducting devices
Wideband
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Summary:A novel compressive cryoreceiver architecture has been proposed combining analog HTS, cryoelectronic, and advanced high-speed GaAs and high-speed/low-power SOI CMOS semiconductor technologies. The proposed receiver will rival the sensitivity of narrowband receivers while providing unprecedented wideband instantaneous frequency coverage with very small size, weight, and power requirements. Future developments will extend the bandwidth capability. HTS tapped-delay-line chirp filters are the enabling technology for instantaneous bandwidths greater than 1 GHz. The filters support dispersive delays as long as 40 ns and time-bandwidth products in excess of 100 using a bonded/thinned-wafer technique to fabricate YBa/sub 2/Cu/sub 3/O/sub 7-/spl part// stripline structures on 125-/spl mu/m-thick, 5-cm-diam LaAlO/sub 3/ substrates. The filters have produced better than -18-dB error sidelobes in a receiver configuration. Preliminary work toward SOI CMOS receiver ASICs is reported. These ASICs will perform pulse data thinning, and binary integration functions. Requirements for A/D converters are discussed.
ISSN:1051-8223
1558-2515
DOI:10.1109/77.621738