VLSI logic and fault simulation on general-purpose parallel computers

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 1993-03, Vol.12 (3), p.446-460
• Main Authors: Mueller-Thuns, R.B., Saab, D.G., Damiano, R.F., Abraham, J.A.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Concurrent computing; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Hardware; Integrated circuits; Logic; Message passing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switches; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.215006

The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines.< >