A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1989-08, Vol.24 (4), p.928-932
Main Authors: Ida, M., Kato, N., Takada, T.
Format: Article
Language:English
Subjects:
Ceramics
Counting circuits
Distributed parameter circuits
Gallium arsenide
Large scale integration
Latches
Multiplexing
Packaging
Pins
Testing
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Summary:A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n/sup +/-layer technology (FG-SAINT process).< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.34073