Yield analysis of large integrated-circuit chips

It has been experimentally observed that integrated-circuit yields decrease as their size increases and various attempts have been made to explain the variation. The authors analyze yield in terms of the geometrical factors involved in producing large chips from circular slices. It is shown that the...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1972-10, Vol.7 (5), p.389-395
Main Authors: Gupta, A., Lathrop, J.W.
Format: Article
Language:English
Subjects:
Circuit topology
Crystallization
Distributed computing
Electronics industry
Extrapolation
Integrated circuit manufacture
Integrated circuit yield
Large scale integration
Silicon
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Summary:It has been experimentally observed that integrated-circuit yields decrease as their size increases and various attempts have been made to explain the variation. The authors analyze yield in terms of the geometrical factors involved in producing large chips from circular slices. It is shown that the qualitatively correct dependence of yield on area is obtained when a defect density that is higher near the outside of the slice is assumed. Results of computer program calculations of the maximum possible number of chips that can be obtained from a slice are given, assuming both random and nonrandom defect distributions.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1972.1052898