Designing the MPC105 PCI bridge/memory controller

The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge...

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Bibliographic Details
Published in:IEEE MICRO 1995-04, Vol.15 (2), p.44-49
Main Authors: Wang, K., Bryant, C., Carlson, M., Elmer, T., Harris, A., Garcia, M., Hui, C.S., Leong, C.K., Reynolds, B., Tang, R., Weber, L., Wenzel, J., Wilson, G., Becker, M.
Format: Article
Language:English
Subjects:
Bridges
Buffer storage
CMOS technology
Computer buffers
Computer memory
Computer peripherals
Control systems
Design optimization
Microprocessors
Packaging
Random access memory
Read only memory
Read-write memory
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Summary:The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM.< >
ISSN:0272-1732
1937-4143
DOI:10.1109/40.372351