A 480-MHz RISC microprocessor in a 0.12-mu m L(eff) CMOStechnology with copper interconnects

This paper describes the performance improvements of a reduced instruction set computer (RISC) microprocessor that has migrated from a 2.5 V technology to a 1.8 V technology. The 1.8 V technology implements copper interconnects and low V(t) field-effect transistors in speed-critical paths and has an...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1998-11, Vol.33 (11), p.1609-1616
Main Authors: Akrout, C, Bialas, J, Canada, M, Cawthron, D, Corr, J, Davari, B, Floyd, R, Geissler, S, Goldblatt, R, Houle, R, Kartschoke, P, Kramer, D, McCormick, P, Rohrer, N, Salem, G, Schulz, R, Su, L, Whitney, L
Format: Article
Language:English
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Summary:This paper describes the performance improvements of a reduced instruction set computer (RISC) microprocessor that has migrated from a 2.5 V technology to a 1.8 V technology. The 1.8 V technology implements copper interconnects and low V(t) field-effect transistors in speed-critical paths and has an L(eff) of 0.12 mum. Global clock latency and skew are improved by using copper wires, and early mode timings are improved by reducing clock skew and adding buffers. These enhancements, along with an environment of 2.0 V, 85 deg C, and with a fast process, produced a 480-MHz RISC microprocessor
ISSN:0018-9200
DOI:10.1109/4.726544