A 2.4-GHz 0.18-mum CMOS self-biased cascode power amplifier

• Published in: IEEE journal of solid-state circuits 2003-08, Vol.38 (8), p.1318-1324
• Main Authors: Sowlati, T, Leenaerts, D M W
• Format: Article
• Language: English
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2003.814417

A two-stage self-biased cascode power amplifier in 0.18-mum CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.