A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integ...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2004-04, Vol.39 (4), p.667-677
Main Authors: McAdams, H.P., Acklin, R., Blake, T., Xiao-Hong Du, Eliason, J., Fong, J., Kraus, W.F., Liu, D., Madan, S., Moise, T., Natarajan, S., Ning Qian, Yunchen Qiu, Remack, K.A., Rodriguez, J., Roscher, J., Seshadri, A., Summerfelt, S.R.
Format: Article
Language:English
Subjects:
Capacitors
Circuits
Copper
Cost function
Density
Ferroelectric films
Ferroelectric materials
Ferroelectricity
Glass
Logic
Nonvolatile memory
Operational amplifiers
Random access memory
State of the art
Voltage
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Summary:A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.825241