A flexible gate array architecture for high-speed and high-density applications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gat...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1996-03, Vol.31 (3), p.430-436
Main Authors: Gallia, J.D., Landers, R.J., Shaw, C.-H., Blake, T.G.W., Banzhaf, W.
Format: Article
Language:English
Subjects:
BiCMOS integrated circuits
CMOS logic circuits
CMOS technology
Delay
Flip-flops
Logic arrays
Logic design
Logic gates
Programmable logic arrays
Wiring
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Summary:A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm/sup 2/ routed density in a 0.5 /spl mu/m TLM CMOS gate array. Compared to previous 5 V 0.7 /spl mu/m gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM's feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.494205