GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers

• Published in: IEEE transactions on electron devices 2000-12, Vol.47 (12), p.2277-2283
• Main Authors: Mochizuki, K., Welty, R.J., Asbeck, P.M., Lutz, C.R., Welser, R.E., Whitney, S.J., Pan, N.
• Format: Article
• Language: English
• Subjects: Annealing; Collectors; Devices; Electric potential; Epitaxial layers; Gallium arsenide; Gallium arsenides; Gallium compounds; Heterojunction bipolar transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.887008

This paper describes a novel heterojunction bipolar transistor (HBT) structure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage V/sub CE,sat/ and the knee voltage V/sub k/. In this device, a thin GaInP layer is used as a tunnel barrier at the base-collector (BC) junction to suppress hole injection into the collector, which results in small V/sub CE,sat/. Collector-up configuration is used because of the observed asymmetry of the band discontinuity between GaInP and GaAs depending on growth direction. To minimize V/sub k/, we optimized the epitaxial layer structure as well as the conditions of ion implantation into the extrinsic emitter and post-implantation annealing. The best results were obtained when a 5-nm-thick 5/spl times/10/sup 17/-cm/sup -3/-doped GaInP tunnel barrier with a 20-nm-thick undoped GaAs spacer was used at the BC junction, and when 2/spl times/10/sup 12/-cm/sup -2/ 50-keV B implantation was employed followed by 10-min annealing at 390/spl deg/C. Fabricated 40/spl times/40-/spl mu/m/sup 2/ C-up TC-HBTs showed almost zero V/sub CE,sat/ (