Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these techn...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2004-08, Vol.51 (8), p.1254-1261
Main Authors: Gallon, C., Reimbold, G., Ghibaudo, G., Bianchi, R.A., Gwoziecki, R., Orain, S., Robilliart, E., Raynaud, C., Dansas, H.
Format: Article
Language:English
Subjects:
Calibration
Devices
Drains
Gates
Isolation technology
MOSFETs
Piezoresistance
Recrystallization
Semiconductor devices
Silicon on insulator technology
Stress
Stresses
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Summary:This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance R/sub sd/. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2004.831358