A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with a...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 1992-07, Vol.39 (7), p.1669-1679
Main Authors: Hayden, J.D., Mele, T.C., Perera, A.H., Burnett, D., Walczyk, F.W., Lage, C.S., Baker, F.K., Woo, M., Paulson, W., Lien, M., See, Y.-C., Denning, D., Cosentino, S.J.
Format: Article
Language:English
Subjects:
BiCMOS integrated circuits
Bipolar transistors
Capacitance
CMOS process
CMOS technology
Cutoff frequency
Delay
MOS devices
MOSFETs
Random access memory
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.141233