An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 1994-04, Vol.29 (4), p.534-538, Article 534
Main Authors: Tsukikawa, Y., Kajimoto, T., Okasaka, Y., Morooka, Y., Furutani, K., Miyamoto, H., Ozaki, H.
Format: Article
Language:English
Subjects:
Capacitors
Character generation
Circuits
Hybrid power systems
MOS devices
Power dissipation
Random access memory
Region 2
Signal generators
Threshold voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.280705