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An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs
An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the...
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| Published in: | IEEE journal of solid-state circuits 1994-04, Vol.29 (4), p.534-538, Article 534 |
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| Main Authors: | , , , , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c306t-31324b266d4e4c2b5384ea3832f93bb6b3d77cc19a029e26b9d1c129a2a147323 |
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| cites | cdi_FETCH-LOGICAL-c306t-31324b266d4e4c2b5384ea3832f93bb6b3d77cc19a029e26b9d1c129a2a147323 |
| container_end_page | 538 |
| container_issue | 4 |
| container_start_page | 534 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 29 |
| creator | Tsukikawa, Y. Kajimoto, T. Okasaka, Y. Morooka, Y. Furutani, K. Miyamoto, H. Ozaki, H. |
| description | An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.< > |
| doi_str_mv | 10.1109/4.280705 |
| format | article |
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This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.280705</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitors ; Character generation ; Circuits ; Hybrid power systems ; MOS devices ; Power dissipation ; Random access memory ; Region 2 ; Signal generators ; Threshold voltage</subject><ispartof>IEEE journal of solid-state circuits, 1994-04, Vol.29 (4), p.534-538, Article 534</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c306t-31324b266d4e4c2b5384ea3832f93bb6b3d77cc19a029e26b9d1c129a2a147323</citedby><cites>FETCH-LOGICAL-c306t-31324b266d4e4c2b5384ea3832f93bb6b3d77cc19a029e26b9d1c129a2a147323</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/280705$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Tsukikawa, Y.</creatorcontrib><creatorcontrib>Kajimoto, T.</creatorcontrib><creatorcontrib>Okasaka, Y.</creatorcontrib><creatorcontrib>Morooka, Y.</creatorcontrib><creatorcontrib>Furutani, K.</creatorcontrib><creatorcontrib>Miyamoto, H.</creatorcontrib><creatorcontrib>Ozaki, H.</creatorcontrib><title>An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.< ></description><subject>Capacitors</subject><subject>Character generation</subject><subject>Circuits</subject><subject>Hybrid power systems</subject><subject>MOS devices</subject><subject>Power dissipation</subject><subject>Random access memory</subject><subject>Region 2</subject><subject>Signal generators</subject><subject>Threshold voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1994</creationdate><recordtype>article</recordtype><recordid>eNqNkE1LxDAYhIMouK6CZ085iZfWvEnaJsfFb1gRRMVbSdJ0N7rb1iRF9t9b6eJBPHgahnlmDoPQMZAUgMhznlJBCpLtoAlkmUigYK-7aEIIiERSQvbRQQhvg-VcwATNZw22de2Ms03EWpn3RDsV8MI21qvYevzp4hIvN9q7Cnf9unPNAhvnTe8irocc0ix5wZePs_twiPZqtQr2aKtT9Hx99XRxm8wfbu4uZvPEMJLHhAGjXNM8r7jlhuqMCW4VE4zWkmmda1YVhTEgFaHS0lzLCgxQqagCXjDKpuh03O18-9HbEMu1C8auVqqxbR9KKmROZAH_ADkVGfABPBtB49sQvK3Lzru18psSSPn9a8nL8dcBTX-hxkUVXdtEr9zqr8LJWHDW2p_dbfgFTsd_Wg</recordid><startdate>19940401</startdate><enddate>19940401</enddate><creator>Tsukikawa, Y.</creator><creator>Kajimoto, T.</creator><creator>Okasaka, Y.</creator><creator>Morooka, Y.</creator><creator>Furutani, K.</creator><creator>Miyamoto, H.</creator><creator>Ozaki, H.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>19940401</creationdate><title>An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs</title><author>Tsukikawa, Y. ; Kajimoto, T. ; Okasaka, Y. ; Morooka, Y. ; Furutani, K. ; Miyamoto, H. ; Ozaki, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-31324b266d4e4c2b5384ea3832f93bb6b3d77cc19a029e26b9d1c129a2a147323</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Capacitors</topic><topic>Character generation</topic><topic>Circuits</topic><topic>Hybrid power systems</topic><topic>MOS devices</topic><topic>Power dissipation</topic><topic>Random access memory</topic><topic>Region 2</topic><topic>Signal generators</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tsukikawa, Y.</creatorcontrib><creatorcontrib>Kajimoto, T.</creatorcontrib><creatorcontrib>Okasaka, Y.</creatorcontrib><creatorcontrib>Morooka, Y.</creatorcontrib><creatorcontrib>Furutani, K.</creatorcontrib><creatorcontrib>Miyamoto, H.</creatorcontrib><creatorcontrib>Ozaki, H.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tsukikawa, Y.</au><au>Kajimoto, T.</au><au>Okasaka, Y.</au><au>Morooka, Y.</au><au>Furutani, K.</au><au>Miyamoto, H.</au><au>Ozaki, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1994-04-01</date><risdate>1994</risdate><volume>29</volume><issue>4</issue><spage>534</spage><epage>538</epage><pages>534-538</pages><artnum>534</artnum><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.< ></abstract><pub>IEEE</pub><doi>10.1109/4.280705</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1994-04, Vol.29 (4), p.534-538, Article 534 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28960971 |
| source | IEEE Electronic Library (IEL) Journals |
| subjects | Capacitors Character generation Circuits Hybrid power systems MOS devices Power dissipation Random access memory Region 2 Signal generators Threshold voltage |
| title | An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs |
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