An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 1999-05, Vol.46 (5), p.927-932
Main Authors: Kuriyama, H., Ashida, M., Tsutsumi, K., Maegawa, S., Maeda, S., Anami, K., Nishimura, T., Kohno, Y., Miyoshi, H.
Format: Article
Language:English
Subjects:
Asymmetry
Devices
Driver circuits
Equivalent circuits
MOSFETs
Power supplies
Power system reliability
Random access memory
Semiconductor devices
Signal to noise ratio
Static random access memory
Thin film transistors
Threshold voltage
Transistors
Writing
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-/spl mu/m design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.760399